Plasma etching is widely used in the fabrication of silicon integrated circuits. One form, often called dielectric etching, etches holes through dielectric or insulating layers such as silicon oxide to provide vertical electrical connections between different levels of the integrated circuit. One dielectric etch process used for advanced integrated circuits forms an inter-level via or other vertical electrical interconnect in a structure utilizing copper metallization and a low-k dielectric. The wafer enters the dielectric etch process having a structure simply illustrated in the cross-sectional view of FIG. 1. A lower-level dielectric layer 10 has a copper contact 12 formed in its surface. The copper contact 12 is likely to be part of a horizontal interconnect formed in a dual-damascene interconnect. It is understood that the copper contact 12 is principally composed of copper with up to 10 at % of intentional dopants or unintended impurities. The lower dielectric layer 10 and the copper contact 12 are covered by a generally planar barrier layer 14, which protects the underlying dielectric and acts as an etch stop layer for the next dielectric layer. An upper dielectric layer 16 is deposited over the barrier layer 14. In a dual-damascene interconnect structure, the upper dielectric layer 16 may be composed of multiple layers separated by an etch stop layer, but the description here will focus on a simpler via structure. The two dielectric layers 10, 16 may be composed of silica or other silicate glass but more advanced devices use low-k dielectric materials ranging from halogen doped silicon dioxide to porous compositions of silicon, carbon, and oxygen, such as BlackDiamond® dielectric available from Applied Materials of Santa Clara, Calif. The barrier layer 14 for more conventional silica dielectrics has typically been silicon nitride, but tantalum nitride is often used for copper metallization, and low-k dielectrics often need the use of more advanced barrier materials, such as SiON or SiC.
A layer of photoresist is deposited over the upper dielectric layer and photographically patterned to form a photomask 18 having an aperture 20 over the area of the intended hole to be etched in the upper dielectric layer 16. At this stage, the wafer is ready for dielectric etching using the photomask 18 to define the etching. The photomask 18 may be a more complex than illustrated, for example, formed of a tri-layer of which only thin upper photoresist layer is photographically patterned to expose an intermediate oxide layer overlying a thicker lower resist layer. The dielectric etch procedure is used to etch the oxide layer, which acts as a hard mask for the thicker lower resist layer. Alternatively, a hard mask layer of, for example, titanium nitride or other material may be intermediate the upper dielectric layer 16 and the photomask 18 and its etching is defined by the photomask 18. Thereafter, the hard mask patterns the etching of the typically softer dielectric materials.
In the dielectric etch process, a plasma etch reactor is used to generate a plasma which, as illustrated in the cross-sectional view of FIG. 2, etches the upper dielectric layer 16 through the photomask 18 to form a via hole 24 extending through the dielectric layer 16 and, at this stage, stopping on the barrier layer 14. For silica-based dielectrics, the etching gas is typically based on a fluorocarbon gas such as C4F6 although often other gases are added. Under the proper conditions, the fluorocarbon plasma etches oxide preferentially to silicon and silicon-based non-oxide materials such as silicon nitride and silicon carbide. Hence, the principal dielectric etch stops on the barrier layer 14.
In a barrier breakthrough etch, as illustrated in the cross-sectional view of FIG. 3, the etching chemistry is changed such that the relatively thin barrier layer 14 is etched away at the bottom of the via hole 24 to expose the copper contact 12. Finally, the remnant photoresist is removed in an ashing step, typically using an oxygen-plasma, so that the upper dielectric layer 16 is exposed for the next processing step. However, there may be a protective layer formed over the upper dielectric layer 16 prior to the dielectric etch to provide extra protection. Thereafter, metallization processing commences including forming a conformal barrier diffusion layer and a copper seed layer, often done by sputtering. Electrochemical plating (ECP) is typically used to fill and overfill the via hole 24 and the chemical mechanical polishing (CMP) removes the copper outside the via hole 24. These latter steps are outside the focus of the invention and will not be further discussed in detail.
In dual-damascene structures, the via hole 24 has a narrow lower portion as illustrated and a wider upper portion or trench. The metallization process simultaneously metallizes both of them to form both the vertical interconnect in the via and a horizontal interconnect or pad in the trench. The dielectric etching of the dual-damascene structure is more complex, but similarly to the described structure it opens the barrier 14 as nearly the last step.
It is greatly desired to perform an integrated dielectric etch process including as many as possible of the described etching steps in a single dielectric etch chamber from the etching of the lower level of the tri-level resist to the ashing. Use of a single chamber reduces the overhead of transferring wafers between multiple dedicated chambers, simplifies the scheduling, and permits the use of fewer expensive etch reactors if the production level is not very high.
An example of a single chamber capable of widely different use is a capacitively coupled plasma etch chamber 30 schematically illustrated in the cross-sectional view of FIG. 4 and described by Hoffman et al. in U.S. Pat. Nos. 6,528,751; 6,853,141; and 6,894,245, collectively Hoffman and all incorporated herein by reference. Hoffman expands upon features of the former in U.S. patent application Ser. No. 11/046,538, filed Jan. 28, 2005. The Enabler chamber available from Applied Materials incorporates parts of the disclosed chamber. The etch chamber 30 separately biases the showerhead and the pedestal supporting the wafer and attempts to decouple the VHF source power applied to the showerhead and producing the plasma from the HF source power applied to the pedestal and producing a DC self bias which affects the energy of an etching ion. The chamber 30 also includes careful selection of source frequency and careful coupling of the VHF power into the chamber, features best described in the cited application. Other features to be briefly described greatly improve the uniformity of etching.
The etch chamber 30 includes a main chamber body 32 including a baffled annular pumping port 34 to a vacuum pump 36 allowing the chamber to be pumped to 100 milliTorr and below. A pedestal electrode 38 supports a wafer 40 be etch processed in opposition to a showerhead 42, which may be made of silicon carbide and which uniformly supplies etching gas into a processing space 44 above the wafer 40. A wafer port 48 with an associated slit valve allows the wafer 38 to be inserted into the chamber 30. An HF power supply 50 RF biases the pedestal electrode 40 through a capacitive matching circuit 52 to produce the DC self bias on the wafer 38. The frequency of the HF power supply 50 may be in the low megahertz range. In some applications not specifically discussed here, two HF power supplies operating respectively at 1.8 MHz and 2.0 MHz may be both input to the matching circuit 52. A broader preferred range for the HF frequency is between 1 and 14 MHz.
The RF biasing of the showerhead 42 is carefully controlled through a coaxial stub 56 including an inner conductor 58 and an outer conductor 60 separated by a insulator 62 and terminated by a short 64 at the end of the stub 56 away from the showerhead 42. The stub 56 has predetermined length, for example, a quarter wavelength of a VHF frequency that provides both high coupling and a wide output impedance. A VHF power supply 68, for example, operating at 162 MHz, is connected through a coaxial cable 70 to the inner conductor 58 at a distance from the short 64 which provides high power coupling. At the showerhead end of the stub 56, the outer conductor 60 is grounded to the chamber body 32 and the inner conductor 58 is connected to a flared conductor 74 which is capacitively coupled to the showerhead 42 through an insulating ring 76 of carefully controlled thickness, which effectively capacitively coupled VHF power onto the showerhead 42 but isolates the VHF biasing of the showerhead 42 from the DC self-biasing of the pedestal electrode 38. A broader preferred range for the VHF is between 150 and 325 MHz.
The showerhead 42 contains a large number of apertures 78 to evenly supply processing gas into the processing space 44. However, the apertures are divided into an annular outer zone 80 and an annular inner zone 82 connected via respective foam-filled manifolds 84, 86 and gas supply lines 88, 90 through a bore 92 within the stub 56 to inner and outer gas supplies 94, 96. Thereby, the process gas may be differentially supplied to inner and outer portions of the wafer 40. A typical diameter of the inner zone 82 is 8.1 inches (206 mm) for a 300 mm wafer. Heating or cooling fluid is supplied to the back of the showerhead 42 and returned therefrom through fluid lines 104 passing through the stub bore 92 and connected to a thermal fluid source 106.
The dual zone showerhead provides a means for tuning the radial distribution of all species of the process gas including neutral atoms or molecules. The ionized species can be separately tuned by two coaxial coils 112, 114 placed in back of the showerhead 42 and supplied with separately controllable amounts of DC current by a plasma steering controller 116 to produce magnetic fields in the processing space 44. The first coil 112 is placed in a radially outer position outside of the showerhead 42 and a short distance above a level of the showerhead 42. The second coil 114 is placed in a radially inner position and a longer distance above the showerhead, preferably adjacent the outside of the top of the flared conductor 72. When approximately equal currents of the same polarity pass through the two coils 112, 114, a cusp-shaped magnetic field is produced having significant radial components in the processing space 44 between the showerhead 42 and the wafer 40, which can steer the ionized components of the process gas.
However, even in the advanced capacitively coupled etch reactor 30, the barrier open step has been found to cause difficulties in the remainder of the integrated dielectric etch process performed in the same chamber. For any production process, the process must remain steady during prolonged operation and not necessitate excessive downtime for chamber cleaning and the like.
Dry cleaning of a chamber with a plasma or an active gas is well known in other contexts. Chambers used for plasma-enhanced chemical vapor deposition (CVD) are nearly as likely to be coated with the CVD material as is the wafer and hence require periodic cleaning. However, cleaning CVD chambers is simple in two respects. The deposited material is well characterized since it is the material being coated on the wafer and hence the cleaning chemistry can be closely tailored to the material being cleaned. Also the chamber coating tends to be deposited nearly uniformly over the interior surface of the chamber. On the other hand, cleaning plasma etch chambers tends to be more difficult. Etching byproducts of somewhat indeterminate composition are likely to deposit on the chamber walls, particularly near the vacuum pumping ports. Since most etching chemistry is based on halogen-containing gases, the chamber walls tend to be coated with metal halides as well as other material. Etching is typically performed through a patterned photomask of carbonaceous composition. The remnants of the photoresist are typically removed in an oxygen-based plasma ashing step. Although in the past the ashing was performed in a separate ashing reactor, the modern trend is to ash within the etching reactor. Further, the byproducts of the main etch often react with the partially etching photoresist and condense on the chamber walls as a polymeric layer. It is known to periodically clean the chamber with a halogen-based cleaning step and fluorine is particularly useful, for example, in a SiF4 cleaning step.
Lu et al. in U.S. Pat. No. 6,352,081 describe cleaning a chamber used for etching copper by a two-step process of an oxidizing etch followed by a fluorocarbon etch.
The cleaning of a plasma etch chamber used to open a dielectric layer over copper or other metal presents distinctive problems since both the dielectric byproducts and the copper byproducts need to be removed and present substantially different chemistries.